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The caching invalidation guidelines from the AMD-Vi specification (48882—Rev 3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction (see stale DMA mappings) if some fields of the DTE are updated but the IOMMU TLB is not flushed. Such stale DMA mappings can point to memory ranges not owned by the guest, thus allowing access to unindented memory regions.
Use CWE-672, Xen vendor hub and Xen product page to widen CVE-2023-34326 into its surrounding weakness, vendor, and product context.
Compare it with CVE-2025-58143, CVE-2025-58142 and CVE-2025-27466 for nearby disclosures in the same product family.